The present invention relates to a semiconductor integrated circuit device and a process for manufacturing the same and, more particularly, to a technique effective when applied to a structure for relieving a fault of a DRAM (Dynamic Random Access Memory).
A DRAM, which is provided with a memory array including a plurality of word lines and a plurality of bit lines so arranged as to intersect each other at a right angle, and a plurality of memory cells arranged at the individual intersections, is equipped with a preparatory redundancy circuit including cells in a portion of the memory array and having the same structure and size as those of normal memory cells, so that a faulty product percentage may be reduced by replacing the lines (word lines or bit lines), for which defective cells are detected at a wafer testing time, by redundant lines.
Japanese Patent Laid-Open No. 4-232688/1992 has disclosed a DRAM which is intended to elongate a refresh cycle. This DRAM includes a plurality of redundant memory cells, a decoder for fetching the addresses of the memory cells and a switch circuit, and the refresh cycle is so adjusted as to become longer for the normal memory cells than that for the defective cells having inferior information holding characteristics. The decoder generates a first output when the fetched address is the one of a normal memory cell, and a second output when the fetched address is the one of a defective cell. The switch circuit is adapted to block an access to the defective cell by allowing the access to the relief cells in response to the first output.
Japanese Patent Laid-Open No. 7-244997/1995 has disclosed a DRAM which can use word lines (word lines connected with a defective cell having inferior information holding characteristics) having a leakage trouble, without increasing the chip size. This DRAM is equipped in its redundancy address decoder with memory means (fuse) for indicating that a trouble of a word line assigned to a redundant one is a leakage trouble, and is given a function to bring the word line and the redundant word line simultaneously into a selected state if the trouble of the word line assigned to the redundant one is the leakage trouble. Consequently even when the redundant word line assigned to the word line having the leakage trouble has a similar leakage trouble, this trouble can be relieved by doubling the substantial information storage capacity of the memory cells.
Japanese Patent Laid-Open No. 1-213900/1989 has disclosed a semiconductor memory device which is equipped with a redundancy circuit having a high-performance sense amplifier connected with relief cells so as to relieve the sense amplifier fault, caused by an erroneous operation due to noise. This sense amplifier is hardly influenced by noise because it is so constructed as to include MOS transistors of high driving ability, which have a larger gate length and width than those of MOS transistors constituting a sense amplifier connected with normal memory cells. As a result, the sense amplifier, connected with the normal memory cells, can be reliably relieved even if it is erroneously operated because of noise.
Japanese Patent Laid-Open No. 4-67669/1992 has disclosed a semiconductor memory device in which the degree of miniaturization (the sizes and spacings of transistors, bit lines and word lines constituting a redundancy circuit) of a redundancy circuit is set larger than that of a main circuit part so as to avoid the fault of the redundancy circuit, as might otherwise be caused by dust or the like.